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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
Rev. 03 -- 25 February 2010 Product data sheet
1. General description
The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT821 bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A. The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers. The device is controlled by the clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable (OE) controls all ten 3-state buffers independent of the register operation. When OE is LOW, the data in the register appears at the outputs. When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will neither drive nor load the bus.
2. Features and benefits
I High-speed parallel registers with positive-edge triggered D-type flip-flops I Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors I Output capability: +64 mA and -32 mA I Power-on 3-state I Power-on reset I Latch-up protection exceeds 500 mA per JESD78B class II level A I ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74ABT821D 74ABT821DB 74ABT821PW -40 C to +85 C -40 C to +85 C -40 C to +85 C SO24 SSOP24 TSSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT137-1 SOT340-1 SOT355-1 Type number
4. Functional diagram
1 13
EN C2 23 22 21 20 19 18 17 16 15 14
001aac735
2
3
4
5
6
7
8
9
10 11
2 3
2D
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 13 1 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 22 21 20 19 18 17 16 15 14
001aac734
4 5 6 7 8 9 10 11
Fig 1. Logic symbol
Fig 2. IEC logic symbol
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
D
D
D
D
D
D
D
D
D
D
CP Q CP 13
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
OE
1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9
001aac736
Fig 3. Logic diagram
74ABT821_3
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Product data sheet
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
74ABT821
OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 CP
001aac733
D8 10 D9 11 GND 12
Fig 4. Pin configuration
5.2 Pin description
Table 2. Symbol OE D0 to D9 GND CP Q0 to Q9 VCC Pin description Pin 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12 13 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 24 Description output enable input (active LOW) data input ground (0 V) clock pulse input (active rising edge) data output supply voltage
74ABT821_3
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
6. Functional description
6.1 Function table
Table 3. Input OE L L L H H
[1]
Function table[1] Internal register CP NC NC D0 to D9 l h X X Dn L H NC NC Dn Output Q0 to Q9 L H NC Z Z load and read register hold disable outputs Operating mode
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don't care; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition.
74ABT821_3
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IOK IO Tj Tstg
[1] [2]
Parameter supply voltage input voltage output voltage input clamping current output clamping current output current junction temperature storage temperature
Conditions
[1]
Min -0.5 -1.2 -0.5 -18 -50 [2]
Max +7.0 +7.0 +5.5 128 150 +150
Unit V V V mA mA mA C C
output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state
[1]
-65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
8. Recommended operating conditions
Table 5. Symbol VCC VI VIH VIL IOH IOL t/V Tamb Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input transition rise and fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 -32 0 -40 Typ Max 5.5 VCC 0.8 64 5 +85 Unit V V V V mA mA ns/V C
74ABT821_3
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
9. Static characteristics
Table 6. Static characteristics Conditions Min VIK VOH input clamping voltage HIGH-level output voltage VCC = 4.5 V; IIK = -18 mA VI = VIL or VIH VCC = 4.5 V; IOH = -3 mA VCC = 5.0 V; IOH = -3 mA VCC = 4.5 V; IOH = -32 mA VOL VOL(pu) II IOFF IO(pu/pd) IOZ LOW-level output voltage power-up LOW-level output voltage input leakage current power-off leakage current power-up/power-down output current VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = GND or 5.5 V VCC = 0 V; VI or VO 4.5 V VCC = 2.0 V; VO = 0.5 V; VI = GND or VCC; OEn HIGH VO = 2.7 V VO = 0.5 V ILO IO ICC output leakage current output current supply current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs disabled ICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND input capacitance output capacitance VI = 0 V or VCC outputs disabled; VO = 0 V or VCC
[4] [3] [2] [1]
Symbol Parameter
25 C Typ -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 Max 0.55 0.55 1.0 100 50 -1.2 2.5 3.0 2.0 -
-40 C to +85 C Unit Min -1.2 2.5 3.0 2.0 Max 0.55 0.55 1.0 100 50 V V V V V V A A A
OFF-state output current VCC = 5.5 V; VI = VIL or VIH -180 5.0 -5.0 5.0 -80 0.5 25 0.5 0.5 50 -50 50 -50 250 38 250 1.5 -180 50 -50 50 -50 250 38 250 1.5 A A A mA A mA A mA
CI CO
[1] [2] [3] [4]
-
4 7
-
-
-
pF pF
For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V 10 %, a transition time of up to 100 s is permitted. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V.
74ABT821_3
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 8. Symbol Parameter Conditions 25 C; VCC = 5.0 V Min tPLH tPHL tPZH tPZL tPHZ tPLZ tsu(H) tsu(L) th(H) th(L) tWH tWL fmax LOW to HIGH propagation delay HIGH to LOW propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay set-up time HIGH set-up time LOW hold time HIGH hold time LOW pulse width HIGH pulse width LOW maximum frequency CP to Qn; see Figure 5 CP to Qn; see Figure 5 OEn to Qn; see Figure 6 OEn to Qn; see Figure 6 OEn to Qn; see Figure 6 OEn to Qn; see Figure 6 Dn to CP; see Figure 7 Dn to CP; see Figure 7 Dn to CP; see Figure 7 Dn to CP; see Figure 7 CP; see Figure 5 CP; see Figure 5 see Figure 5 2.1 2.8 1.0 2.2 2.7 2.3 2.1 2.1 1.3 1.3 2.9 3.8 125 Typ 4.1 4.6 3.0 4.1 4.7 4.6 0.5 0.3 0 -0.3 1.8 2.8 185 Max 5.6 6.2 4.5 5.6 6.2 6.1 -40 C to +70 C; Unit VCC = 5.0 V 0.5 V Min 2.1 2.8 1.0 2.2 2.7 2.3 2.1 2.1 1.3 1.3 2.9 3.8 125 Max 6.2 6.7 5.3 6.3 6.7 6.5 ns ns ns ns ns ns ns ns ns ns ns ns MHz
11. Waveforms
1/f max VI CP input GND t WH t PHL VOH Qn output VOL VM
001aac445
VM
t WL t PLH
VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5.
Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and maximum clock (CP) frequency
74ABT821_3
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
VI OE input GND tPLZ 3.5 V output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
001aal299
VM
tPZL
VM VOL + 0.3 V tPZH VOH - 0.3 V VM
VM = 1.5 V. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
3-state output (Qn) enable and disable times
Vl Dn input GND t su(H) Vl CP input GND VM VM
001aac738
VM
VM t h(H)
VM t su(L)
VM t h(L)
VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7.
Set-up and hold times data input (Dn) to clock (CP)
74ABT821_3
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
VI negative pulse 0V
tW 90 % VM 10 % tf tr VM 10 % tr tf 90 % VM 10 % tW
001aai298
90 %
VEXT VCC VI VO DUT
RT CL RL RL
G
VI positive pulse 0V
90 % VM 10 %
mna616
a. Input pulse definition
Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance.
b. Test circuit
RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times.
Fig 8. Table 8. Input VI 3.0 V
Test circuit for measuring switching times Test data Load fI 1 MHz tW 500 ns tr, tf 2.5 ns CL 50 pF RL 500 VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V
74ABT821_3
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Product data sheet
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9.
74ABT821_3
Package outline SOT137-1 (SO24)
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Product data sheet
Rev. 03 -- 25 February 2010
10 of 16
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT340-1 (SSOP24)
74ABT821_3 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
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NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT355-1 (TSSOP24)
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
13. Abbreviations
Table 9. Acronym BiCMOS DUT ESD HBM MM Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model
14. Revision history
Table 10. Revision history Release date 20100225 Data sheet status Product data sheet Change notice Supersedes 74ABT821_2 Document ID 74ABT821_3 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 "Ordering information" and Section 12 "Package outline". Product specification Product specification 74ABT821 -
74ABT821_2 74ABT821
20050412 19950906
74ABT821_3
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Product data sheet
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the
(c) NXP B.V. 2010. All rights reserved.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
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74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT821_3
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10-bit D-type flip-flop; positive-edge trigger; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 February 2010 Document identifier: 74ABT821_3

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